The present disclosure relates to a differential ring oscillation circuit, a device including the differential ring oscillation circuit, and an oscillation control method of controlling the differential ring oscillation circuit.
A differential ring oscillation circuit including delay circuits at even stages has been used as a clock generation circuit in various devices. For example, a differential ring oscillation circuit including delay circuits at even stages has been used as a clock generation circuit that supplies a clock to a plurality of flip-flops which are included in a wired communication device and are connected in parallel. In the flip-flops which are included in the wired communication device and are connected in parallel, a multi-phase clock shifted by ½ period or ¼ period from a reference phase is necessary. In an orthogonal modulator or an orthogonal demodulator included in a wireless communication device, a multi-phase clock shifted by ¼ period from a reference phase is also necessary. When the multi-phase clock shifted by ½ period or ¼ period is necessary, a differential ring oscillation circuit including delay circuits at even stages is used.
Meanwhile, such an oscillation circuit may enter a state called deadlock due to an oscillation state fault, and thus a clock may not be generated in some cases.
Japanese Unexamined Patent Application Publication No. 2009-200662 discloses a technology for operating a deadlock detection circuit and recovering a normal oscillation state in a phase locked loop (PLL) circuit using an oscillation circuit, when a frequency of a feedback signal exceeds a threshold value.